Ph.D., Electrical Engineering, the University of Texas at Arlington. Dissertation: “Emerging Energy-efficient Scalable Interconnect Design for VLSI Logic and Memory Applications”.
M.S., Electrical Engineering, Columbia University.
Learn more →Z. Pei*, S. Lu*, L. Shang, S. Jung, Q. Liang, and C. Pan, "Graphene-based interconnect exploration for FPGA design and optimization towards the end of the roadmap," ACM Transactions on Design Automation of Electronic Systems, 2026. DOI: 10.1145/3810248
Z. Pei, H.-H. Liu, M. Mayahinia, M. Tahoori, F. Catthoor, Z. Tokei, P. Dubey, and C. Pan, “Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025. DOI: 10.1109/TVLSI.2025.3595818
Z. Pei, H.-H. Liu, M. Mayahinia, M. B. Tahoori, F. Catthoor, Z. Tőkei, D. B. Abdi, J. Myers, and C. Pan, “Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2024. DOI: 10.1109/TCSI.2024.3438164
Z. Pei, M. Mayahinia, H.-H. Liu, M. Tahoori, F. Catthoor, Z. Tokei, and C. Pan, “Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes,” IEEE Transactions on Electron Devices, vol. 70, pp. 230-238, 2022. DOI: 10.1109/TED.2022.3225512
Z. Pei, A. Dutta, L. Shang, S. Jung, and C. Pan, “Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials,” IEEE Transactions on Electron Devices, vol. 68, pp. 3513-3519, 2021. DOI: 10.1109/TED.2021.3077210
Z. Pei, L. Shang, S. Jung, and C. Pan, “Deep Pipeline Circuit for Low-Power Spintronic Devices,” IEEE Transactions on Electron Devices, vol. 68, pp. 1962-1968, 2021. DOI: 10.1109/TED.2021.3059601
About
Born into an ordinary family, Dr. Pei developed resilience early in life. Prior to university, he combined rigorous academic preparation with a significant personal transformation through long-distance running, cultivating discipline and endurance, qualities that later underpinned his academic and industrial achievements.
During his Ph.D., he collaborated with the IMEC to develop the CACTI++ framework, which bridges key gaps in rapid EDA-based co-design and co-optimization from the transistor to the system level. He was a senior design engineer in IP Group R&D for tapeout at Cadence Design Systems, Inc. for four years, gaining expertise in the full RTL-to-GDSII workflow.